In the global market, manufacturers of mass products must offer high quality devices at a low price. It is thus important to improve yield and process efficiency to minimize production costs. This holds especially true in the field of semiconductor fabrication, where it is essential to combine cutting-edge technology with volume production techniques. It is the goal of semiconductor manufacturers to reduce the consumption of raw materials and consumables while at the same time improving process tool utilization. Improving process tool utilization is especially important in modern semiconductor facilities where extremely costly equipment often represents the dominant part of the total production costs.
Integrated circuits are typically manufactured in automated or semi-automated facilities by passing substrates through a large number of process steps to complete the devices. The number and the type of process steps a semiconductor device has to go through may depend on the specifics of the semiconductor device to be fabricated. For instance, a sophisticated Central Processing Unit (CPU) may require several hundred process steps, each of which has to be carried out within specified process margins to fulfill the specifications for the device under consideration.
In a semiconductor facility, a plurality of different product types are usually manufactured at the same time, such as memory chips of different design and storage capacity, CPUs of different design and operating speed, and the like. The number of different product types may even reach a hundred or more in production lines for manufacturing ASICs (Application Specific ICs). Each of the different product types may require a specific process flow, and require different mask sets for lithography and specific settings in various process tools, such as deposition tools, etch tools, implantation tools, chemical mechanical polishing (CMP) tools and the like. Consequently, a plurality of different tool parameter settings and product types may be encountered simultaneously in a manufacturing environment. Thus, a mixture of product types, such as test and development products, pilot products, and different versions of products, at different manufacturing stages, may be present in the manufacturing environment at a time. Further, the composition of the mixture may vary over time depending on economic constraints and the like, since the dispatching of non-processed substrates into the manufacturing environment may depend on various factors, such as the ordering of specific products, a variable degree of research and development efforts and the like. Thus, the various product types may have to be processed with varying priority to meet requirements imposed by specific economic or other constraints.
A typical method of prioritizing dispatch among the devices involves calculating a traditional critical ratio for semiconductor substrates that are grouped into lots. The traditional critical ratio is a ratio of the time remaining until the scheduled shipment of the devices to the processing time remaining to be performed before the devices are completed. When multiple lots are waiting for processing on a given tool, the lot with the smallest traditional critical ratio is typically selected for processing when the tool is next available. The traditional critical ratio is sensitive to delays in processing near the end of a production cycle of a semiconductor device, but is not very sensitive to delays in processing near the beginning or middle of the production cycle. Although the traditional critical ratio is suitable for its intended purpose, the need for improved lot dispatching methods in complex semiconductor manufacturing facilities is ever present.
As such, it is desirable to provide improved methods and media for lot dispatching during semiconductor device fabrication. Furthermore, other desirable features and characteristics of the inventive subject matter will become apparent from the subsequent detailed description of the inventive subject matter and the appended claims, taken in conjunction with the accompanying drawings and this background of the inventive subject matter.